- Accelerating TFHE implementation
- Currently I an working on designing a hardware to accelerate TFHE’s implementation.
- Dataflow analysis and optimization of KeySwitching algorithm for Homomorphic encryption
- This project was funded by DARPA, under the Data Protection in Virtual Environments (DPRIVE) program, contract HR0011-21-9-0003.
- Description: One of the main computational bottlnecks in HE is the key-switching workload. In this research we present a novel approach to improve key-switching performance by optimizing the dataflow and capturing on-chip reuse with far less SRAM and simultaneously reducing the off-chip bandwidth requirement.
- Vector Processor for Ring Learning With Errors (RLWE)-based algorithms, named RPU.
- This project was funded by DARPA, under the Data Protection in Virtual Environments (DPRIVE) program, contract HR0011-21-9-0003.
- Description: We present a novel vector Instruction Set Architecture (ISA) and microarchitecture for accelerating the ring-based computations of RLWE, named B512. We then propose the ring processing unit (RPU), a high-performance, modular imlpementation of B512. Having an ISA, instead of a fixed hardware design increases the flexibility to support the evolving RLWE-based workloads.
- Paper: RPU: The Ring Processing Unit
M. Sc. Project
- FPGA-based Multi-precision Accelerator for Deep Neural Networks
B. Sc. Projects
- Implementation of a Tracking System Using LoRaWAN Protocol
- Researcher in Digital Systems Design Lab
